Structure and formation method of semiconductor device structure with nanowire

ABSTRACT

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate including a first fin portion and a first nanowire over the first fin portion. The first nanowire has a polygonal cross-section. The semiconductor device structure also includes a first gate structure surrounding the first nanowire, and two first source/drain portions adjacent to the first nanowire.

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims the benefit of U.S. Provisional Application No.62/583,065, entitled “STRUCTURE AND FORMATION METHOD OF SEMICONDUCTORDEVICE STRUCTURE WITH NANOWIRES” filed on Nov. 8, 2017, the entirety ofwhich is incorporated herein by reference.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. Technological advances in IC materials and design have producedgenerations of ICs. Each generation has smaller and more complexcircuits than the previous generation.

In the course of IC evolution, functional density (i.e., the number ofinterconnected devices per chip area) has generally increased whilegeometric size (i.e., the smallest component (or line) that can becreated using a fabrication process) has decreased. This scaling-downprocess generally provides benefits by increasing production efficiencyand lowering associated costs.

Such scaling down has also increased the complexity of processing andmanufacturing ICs and, for these advances to be realized, similardevelopments in IC processing and manufacturing are needed. For example,a three-dimensional transistor, such as a semiconductor device withnanowires, has been introduced to replace planar transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It shouldbe noted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A-1P are schematic views of various stages of a process forforming a semiconductor device structure, in accordance with someembodiments.

FIGS. 2A-2C are schematic views of various stages of a process forforming a semiconductor device structure, in accordance with someembodiments.

FIG. 2D is a schematic view of a nanowire in accordance with someembodiments of the present disclosure.

FIG. 2E is a cross-sectional view of a nanowire in accordance with someembodiments of the present disclosure.

FIG. 2F is a cross-sectional view of a nanowire in accordance with someembodiments of the present disclosure.

FIG. 3A is a cross-sectional view of a nanowire in accordance with someembodiments of the present disclosure.

FIG. 3B is a cross-sectional view of a nanowire in accordance with someembodiments of the present disclosure.

FIGS. 4A-4C are schematic views of various stages of a process forforming a semiconductor device structure, in accordance with someembodiments.

FIGS. 5A-5B are schematic views of various stages of a process forforming a semiconductor device structure, in accordance with someembodiments.

FIG. 6A is a top view of a semiconductor device structure in accordancewith some cases.

FIG. 6B is a top view of a semiconductor device structure in accordancewith some embodiments of the present disclosure.

FIG. 6C is a top view of a semiconductor device structure in accordancewith some embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, theperformance of a first process before a second process in thedescription that follows may include embodiments in which the secondprocess is performed immediately after the first process, and may alsoinclude embodiments in which additional processes may be performedbetween the first and second processes. Various features may bearbitrarily drawn in different scales for the sake of simplicity andclarity. Moreover, the formation of a first feature over or on a secondfeature in the description that follows may include embodiments in whichthe first and second features are formed in direct contact, and may alsoinclude embodiments in which additional features may be formed betweenthe first and second features, such that the first and second featuresmay not be in direct contact. In some embodiments, the presentdisclosure may repeat reference numerals and/or letters in some variousexamples. This repetition is for the purpose of simplicity and clarityand does not in itself dictate a relationship between some variousembodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Some embodiments of the disclosure are described. Additional operationscan be provided before, during, and/or after the stages described inthese embodiments. Some of the stages that are described can be replacedor eliminated for different embodiments. Additional features can beadded to the semiconductor device structure. Some of the featuresdescribed below can be replaced or eliminated for different embodiments.Although some embodiments are discussed with operations performed in aparticular order, these operations may be performed in another logicalorder.

The gate all around (GAA) transistor structures may be patterned usingany suitable method. For example, the structures may be patterned usingone or more photolithography processes, including double-patterning ormulti-patterning processes. Generally, double-patterning ormulti-patterning processes combine photolithography and self-alignedprocesses, allowing patterns to be created that have, for example,pitches smaller than what is otherwise obtainable using a single, directphotolithography process. For example, in one embodiment, a sacrificiallayer is formed over a substrate and patterned using a photolithographyprocess. Spacers are formed alongside the patterned sacrificial layerusing a self-aligned process. The sacrificial layer is then removed, andthe remaining spacers may then be used to pattern the GAA structure.

FIGS. 1A-1P are cross-sectional views of various stages of a process forforming a semiconductor device structure, in accordance with someembodiments. As shown in FIG. 1A, a semiconductor substrate 102 isreceived or provided, in accordance with some embodiments. In someembodiments, the semiconductor substrate 102 is a bulk semiconductorsubstrate, such as a semiconductor wafer. For example, the semiconductorsubstrate 102 is a silicon wafer. The semiconductor substrate 102 mayinclude silicon or another elementary semiconductor material such asgermanium. In some other embodiments, the semiconductor substrate 102includes a compound semiconductor. The compound semiconductor mayinclude gallium arsenide, silicon carbide, indium arsenide, indiumphosphide, another suitable material, or a combination thereof.

In some embodiments, the semiconductor substrate 102 includes asemiconductor-on-insulator (SOI) substrate. The SOI substrate may befabricated using a separation by implantation of oxygen (SIMOX) process,a wafer bonding process, another applicable method, or a combinationthereof.

In some embodiments, the semiconductor substrate 102 is an un-dopedsubstrate. However, in some other embodiments, the semiconductorsubstrate 102 is a doped substrate such as a P-type substrate or anN-type substrate.

In some embodiments, the semiconductor substrate 102 includes variousdoped regions (not shown) depending on design requirements of thesemiconductor device. The doped regions include, for example, p-typewells and/or n-type wells. In some embodiments, the doped regions aredoped with p-type dopants. For example, the doped regions are doped withboron or BF₂. In some embodiments, the doped regions are doped withn-type dopants. For example, the doped regions are doped with phosphoror arsenic. In some embodiments, some of the doped regions are p-typedoped, and the other doped regions are n-type doped.

Still referring to FIG. 1A, a stacked-layer structure 104 is formed overthe semiconductor substrate 102, in accordance with some embodiments. Asshown in FIG. 1A, the stacked-layer structure 104 includes one or moreof the first semiconductor material layers 106 and one or more of thesecond semiconductor material layers 108 alternately stacked verticallyover the semiconductor substrate 102, in accordance with someembodiments. Although the stacked-layer structure 104 shown in FIG. 1Aincludes four second semiconductor material layers 108 and four firstsemiconductor material layers 106, the embodiments of the presentdisclosure are not limited thereto. In some other embodiments, thestacked-layer structure 104 includes one first semiconductor materiallayers 106 and one second semiconductor material layers 108 verticallystacked over the semiconductor substrate 102.

In some embodiments, the second semiconductor material layer 108 and thefirst semiconductor material layer 106 are independently made ofsilicon, silicon germanium, germanium tin, silicon germanium tin,gallium arsenide, indium gallium arsenide, indium arsenide, anothersuitable material, or a combination thereof. In some embodiments, thematerial of second semiconductor material layer 108 is different thanthe material of first semiconductor material layer 106. In someembodiments, the second semiconductor material layer 108 is made ofsilicon germanium, whereas the first semiconductor material layer 106 ismade of silicon, and the semiconductor substrate 102 is made of silicon.In some embodiments, the second semiconductor material layer 108 is madeof indium gallium arsenide, whereas the first semiconductor materiallayer 106 is made of gallium arsenide, and the semiconductor substrate102 is made of gallium arsenide.

In some embodiments, the first semiconductor material layers 106 and thesecond semiconductor material layers 108 are formed using an epitaxialgrowth process. Each of the first semiconductor material layers 106 andthe second semiconductor material layers 108 may be formed using aselective epitaxial growth (SEG) process, a chemical vapor deposition(CVD) process (e.g., a vapor-phase epitaxy (VPE) process, a low-pressureCVD (LPCVD) process, and/or an ultra-high vacuum CVD (UHV-CVD) process),a molecular beam epitaxy process, another applicable process, or acombination thereof. In some embodiments, the first semiconductormaterial layers 106 and the second semiconductor material layers 108 aregrown in-situ in the same process chamber.

Afterwards, as shown in FIG. 1B, multiple recesses (or trenches) 110 areformed to pattern the first semiconductor material layers 106, thesecond semiconductor material layers 108, and the upper portion of thesemiconductor substrate 102, in accordance with some embodiments. Insome embodiments, multiple photolithography processes and etchingprocesses are performed to form the recesses 110. The recess 110 may beused to separate two neighboring field effect transistors (FETs).

As a result, the patterned semiconductor substrate 102 includes a baseportion 112, a first fin portion 114 over the base portion 112 and asecond fin portion 116 over the base portion 112 and adjacent to eachother, in accordance with some embodiments. As shown in FIG. 1B, thefirst fin portion 114 and the second fin portion 116 are between therecesses 110, in accordance with some embodiments.

As shown in FIG. 1B, the patterned first semiconductor material layers106 and the patterned second semiconductor material layers 108 form thefirst semiconductor layers 118 and the second semiconductor layers 120respectively, in accordance with some embodiments. In some embodiments,the first semiconductor layers 118 and the second semiconductor layers120 form two stack structures 122 over the first fin portion 114 and thesecond fin portion 116 respectively. As shown in FIG. 1B, the firstsemiconductor layers 118 and the second semiconductor layers 120 of thestack structure 122 vertically stacked over the first fin portion 114and/or the second fin portion 116, in accordance with some embodiments.

In some embodiments, the second semiconductor layer 120 and the firstsemiconductor layer 118 are independently made of silicon, silicongermanium, germanium tin, silicon germanium tin, gallium arsenide,indium gallium arsenide, indium arsenide, another suitable material, ora combination thereof. In some embodiments, the material of secondsemiconductor layer 120 is different than the material of firstsemiconductor layer 118. In some embodiments, the second semiconductorlayer 120 is made of silicon germanium, whereas the first semiconductorlayer 118 is made of silicon, and the semiconductor substrate 102 ismade of silicon. In some embodiments, the second semiconductor layer 120is made of indium gallium arsenide, whereas the first semiconductorlayer 118 is made of gallium arsenide, and the semiconductor substrate102 is made of gallium arsenide. In some embodiments, the thickness ofthe second semiconductor layer 120 is substantially equal to thethickness of the first semiconductor layer 118.

As shown in FIG. 1B, one or more isolation structures including anisolation structure 124 are formed over the semiconductor substrate 102and formed in the recesses 110 to surround the first fin portion 114 andthe second fin portion 116, in accordance with some embodiments. Theisolation structure 124 is adjacent to the first fin portion 114 and thesecond fin portion 116. In some embodiments, the isolation structure 124continuously surrounds the first fin portion 114 and the second finportion 116.

The isolation structure 124 is used to define and electrically isolatevarious device elements formed in and/or over the semiconductorsubstrate 102. In some embodiments, the isolation structure 124 includesa shallow trench isolation (STI) feature, a local oxidation of silicon(LOCOS) feature, another suitable isolation structure, or a combinationthereof.

In some embodiments, the isolation structure 124 has a multi-layerstructure. In some embodiments, the isolation structure 124 is made of adielectric material. The dielectric material may include silicon oxide,silicon nitride, silicon oxynitride, fluoride-doped silicate glass(FSG), low-K dielectric material, another suitable material, or acombination thereof. In some embodiments, a first STI liner 126 and asecond STI liner 128 are formed to reduce crystalline defects at theinterface between the semiconductor substrate 102 and the isolationstructure 124. In some embodiments of the present disclosure, the firstSTI liner 126 is formed over the sidewalls of the first fin portion 114and the second fin portion 116 and over the base portion 112, and thesecond STI liner 128 is formed over the first STI liner 126. The firstSTI liner 126 and the second STI liner 128 may also be used to reducecrystalline defects at the interface between the fin portions 106 andthe isolation structure 124.

In some embodiments, two STI liner material layers and a dielectriclayer is deposited to cover the semiconductor substrate 102 and thestack structure 122 using a chemical vapor deposition (CVD) process, aspin-on process, another applicable process, or a combination thereof.The chemical vapor deposition may include, but is not limited to, lowpressure chemical vapor deposition (LPCVD), low temperature chemicalvapor deposition (LTCVD), rapid thermal chemical vapor deposition(RTCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layerdeposition (ALD), or any other suitable method. The dielectric layercovers the first fin portion 114 and the second fin portion 116 andfills the recesses 110 between the fin portions 106.

Afterwards, in some embodiments, a planarization process is performed tothin down the two STI liner material layers and the dielectric layer.For example, the dielectric layer is thinned until the stack structure122 is exposed. The planarization process may include a chemicalmechanical polishing (CMP) process, a grinding process, a dry polishingprocess, an etching process, another applicable process, or acombination thereof. Afterwards, the two STI liner material layers andthe dielectric layer are etched back to be below the top of the stackstructure 122. As a result, the first STI liner 126, the second STIliner 128 and the isolation structure 124 are formed.

Afterwards, as shown in FIG. 1C, a dummy gate dielectric layer 130 isdeposited covering the stack structure 122 and the isolation structure124, in accordance with some embodiments.

In some embodiments, the dummy gate dielectric layer 130 is made ofsilicon oxide, silicon nitride, silicon oxynitride, the high-k material,another suitable dielectric material, or a combination thereof. In someembodiments, the high-k material may include, but is not limited to,metal oxide, metal nitride, metal silicide, transition metal oxide,transition metal nitride, transition metal silicide, transition metaloxynitride, metal aluminate, zirconium silicate, zirconium aluminate.For example, the material of the high-k material may include, but is notlimited to, LaO, AlO, ZrO, TiO, Ta₂O₅, Y₂O₃, SrTiO₃(STO), BaTiO₃(BTO),BaZrO, HfO₂, HfO₃, HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO,HfTiO, HfTaTiO, HfAlON, (Ba,Sr)TiO₃(BST), Al₂O₃, another suitable high-kdielectric material, or a combination thereof.

In some embodiments, the applicable deposition methods for depositingthe dummy gate dielectric layer 130 include a chemical vapor deposition(CVD) process, an atomic layer deposition (ALD) process, a thermaloxidation process, a spin-on coating process, other applicableprocesses, and combinations thereof.

Afterwards, as shown in FIG. 1D, a dummy gate electrode 132 is formedover the dummy gate dielectric layer 130, in accordance with someembodiments.

In some embodiments, the dummy gate electrode 132 is made ofpolysilicon, a metal material, another suitable conductive material, ora combination thereof. In some embodiments, the metal material mayinclude, but is not limited to, copper, aluminum, tungsten, molybdenum,titanium, tantalum, platinum, or hafnium. In some embodiments, the dummygate electrode 132 will be replaced with another conductive materialsuch as a metal material in subsequent processes.

Still referring to FIG. 1D, a mask element 136 is formed over the dummygate electrode 132, in accordance with some embodiments. In someembodiments, the mask element 136 is made of silicon oxide, siliconnitride, silicon oxynitride or another suitable material.

In some embodiments of the present disclosure, a gate electrode materiallayer (not shown) is deposited over the dummy gate dielectric layer 130.In some embodiments the gate electrode material layer is deposited byusing applicable deposition methods.

In some embodiments, the applicable deposition methods for depositingthe gate electrode material layer include a chemical vapor deposition(CVD) process, a physical vapor deposition (PVD) process, and otherapplicable methods.

Afterwards, according to some embodiments of the present disclosure, themask element 136 is formed over the dummy gate electrode 132, inaccordance with some embodiments. In some embodiments, the applicabledeposition methods for depositing the mask element 136 include achemical vapor deposition (CVD) process, an atomic layer deposition(ALD) process, a thermal oxidation process, a spin-on coating process,other applicable processes, and combinations thereof.

Afterwards, according to some embodiments of the present disclosure, byusing the mask element 136 as an etching mask, the gate electrodematerial layer is patterned to form the dummy gate electrode 132.

As shown in FIG. 1D, the dummy gate dielectric layer 130 and the dummygate electrode 132 form a dummy gate structure 134, in accordance withsome embodiments. As shown in FIG. 1D, the dummy gate structure 134covers a portion of the stack structure 122, in accordance with someembodiments. As shown in FIG. 1D, the dummy gate structure 134 exposesanother portion of the stack structure 122, in accordance with someembodiments.

In some embodiments, a spacer layer 138 is deposited over thesemiconductor substrate 102, the stack structure 122, the dummy gatestructure 134 and the mask element 136. In some embodiments, the spacerlayer 138 is made of silicon nitride, silicon oxynitride, siliconcarbide, another suitable material, or a combination thereof. The spacerlayer 138 may be deposited using a CVD process, a PVD process, a spin-oncoating process, another applicable process, or a combination thereof.

Afterwards, as shown in FIG. 1E, an etching process, such as ananisotropic etching process, is performed to partially remove the spacerlayer 138. As a result, the remaining portions of the spacer layer 138over the sidewalls of the dummy gate structure 134 form the spacerelements 140. As shown in FIG. 1E, the spacer elements 140 are formedover sidewalls of the dummy gate structure 134, in accordance with someembodiments. In some embodiments, the spacer elements 140 are made ofsilicon nitride, silicon oxynitride, silicon carbide, another suitablematerial, or a combination thereof.

Still referring to FIG. 1E, the first fin portion 114 and the second finportion 116 has channel regions 142 and source/drain regions 144, inaccordance with some embodiments. As shown in FIG. 1E, the channelregions 142 are the regions covered by the dummy gate structure 134 andthe spacer elements 140, in accordance with some embodiments. As shownin FIG. 1E, the source/drain regions 144 are the regions exposed by thedummy gate structure 134 and the spacer elements 140, in accordance withsome embodiments.

In some embodiments of the present disclosure, the spacer elements 140expose the stack structures 122 in the source/drain regions 144, inaccordance with some embodiments.

Afterwards, as shown in FIG. 1F, a mask element 146 is formed over thedummy gate structure 134, the spacer elements 140, the mask element 136and the stack structures 122 which are over the first fin portion 114,in accordance with some embodiments. As shown in FIG. 1F, the maskelement 146 exposes the stack structures 122 over the second fin portion116, in accordance with some embodiments.

Afterwards, as shown in FIG. 1F, an etching process, such as ananisotropic etching process, is performed to remove the secondsemiconductor layers 120 over the second fin portion 116 in thesource/drain regions 144 and form spaces between the first semiconductorlayers 118, in accordance with some embodiments. As shown in FIG. 1F,the second semiconductor layers 120 over the second fin portion 116 inthe channel regions 142 remain, in accordance with some embodiments.

Afterwards, as shown in FIG. 1F, source/drain portions 148 are formed inthe stack structure 122 in the source/drain region 144 over the secondfin portion 116, in accordance with some embodiments. As shown in FIG.1F, the source/drain portions 148 are between the second semiconductorlayers 120 in the channel regions 142, in accordance with someembodiments. As shown in FIG. 1F, the source/drain portions 148 areadjacent to the second semiconductor layers 120 in the channel regions142, in accordance with some embodiments.

In some embodiments, the source/drain portions 148 are an n-typesemiconductor material. The source/drain portions 148 may includeepitaxially grown silicon, epitaxially grown silicon phosphide (SiP), oranother applicable epitaxially grown semiconductor material. Thesource/drain portions 148 are not limited to being an n-typesemiconductor material. In some other embodiments, the source/drainportions 148 are made of a p-type semiconductor material. For example,the source/drain portions 148 may include epitaxially grown silicongermanium.

In some embodiments, a semiconductor material is epitaxially grown inthe space between the first semiconductor layers 118 to form thesource/drain portions 148 over the second fin portion 116. In someembodiments, the source/drain portions 148 are formed by using aselective epitaxial growth (SEG) process, a CVD process (e.g., avapor-phase epitaxy (VPE) process, a low pressure chemical vapordeposition (LPCVD) process, and/or an ultra-high vacuum CVD (UHV-CVD)process), a molecular beam epitaxy process, another applicable process,or a combination thereof.

Afterwards, the mask element 146 is removed, in accordance with someembodiments. Afterwards, other source/drain portions 150 are formed overthe first fin portion 114 by a process that is similar to the onementioned above, in accordance with some embodiments. It should be notedthat the source/drain portions 150 are not shown in FIG. 1F, but areshown in FIG. 4A. As shown in FIG. 4A, source/drain portions 150 areformed in the stack structure 122 in the source/drain region 144 overthe first fin portion 114, in accordance with some embodiments. As shownin FIG. 4A, the source/drain portions 150 are between the firstsemiconductor layers 118 in the channel regions 142, in accordance withsome embodiments. As shown in FIG. 4A, the source/drain portions 150 areadjacent to the first semiconductor layers 118 in the channel regions142, in accordance with some embodiments.

In some embodiments, the source/drain portions 150 are an n-typesemiconductor material. The source/drain portions 150 may includeepitaxially grown silicon, epitaxially grown silicon phosphide (SiP), oranother applicable epitaxially grown semiconductor material. Thesource/drain portions 150 are not limited to being an n-typesemiconductor material. In some other embodiments, the source/drainportions 150 are made of a p-type semiconductor material. For example,the source/drain portions 150 may include epitaxially grown silicongermanium.

In some embodiments, a mask element (not shown) is formed to cover thestack structures 122 over the second fin portion 116 and to expose thestack structures 122 over the first fin portion 114, in accordance withsome embodiments. Afterwards, an etching process, such as an anisotropicetching process, is performed to remove the first semiconductor layers118 over the first fin portion 114 in the source/drain regions 144 andto form spaces between the second semiconductor layers 120, inaccordance with some embodiments.

Afterwards, in some embodiments, a semiconductor material is epitaxiallygrown in the space between the second semiconductor layers 120 to formthe source/drain portions 150 over the first fin portion 114. In someembodiments, the source/drain portions 150 are formed by using aselective epitaxial growth (SEG) process, a CVD process (e.g., avapor-phase epitaxy (VPE) process, a low pressure chemical vapordeposition (LPCVD) process, and/or an ultra-high vacuum CVD (UHV-CVD)process), a molecular beam epitaxy process, another applicable process,or a combination thereof.

Afterwards, as shown in FIG. 1G, an etch stop layer 152 is conformallydeposited over the dummy gate structure 134, the spacer elements 140,the mask element 136 and the stack structures 122, in accordance withsome embodiments.

In some embodiments, the etch stop layer 152 is made of silicon nitride,silicon oxynitride, silicon carbide, another suitable material, or acombination thereof. In some embodiments, the applicable depositionmethods for depositing the etch stop layer 152 includes a chemical vapordeposition (CVD) process, an atomic layer deposition (ALD) process, aspin-on coating process, other applicable processes, and combinationsthereof.

Afterwards, as shown in FIG. 1H, an interlayer dielectric layer 154 issubsequently formed over the etch stop layer 152, in accordance withsome embodiments. In some embodiments, the interlayer dielectric layer154 is made of silicon oxide, silicon oxynitride, borosilicate glass(BSG), phosphoric silicate glass (PSG), borophosphosilicate glass(BPSG), fluorinated silicate glass (FSG), low-k material, porousdielectric material, another suitable material, or a combinationthereof. In some embodiments, the interlayer dielectric layer 154 isdeposited using a CVD process, an ALD process, a spin-on process, aspray coating process, another applicable process, or a combinationthereof.

In some embodiments, a dielectric layer is deposited over the etch stoplayer 152 using a chemical vapor deposition (CVD) process, a spin-onprocess, another applicable process, or a combination thereof. In someembodiments, a planarization process is performed to thin down thedielectric layer. For example, the dielectric layer is thinned until thedummy gate electrode 132 is exposed. The planarization process mayinclude a chemical mechanical polishing (CMP) process, a grindingprocess, a dry polishing process, an etching process, another applicableprocess, or a combination thereof. As a result, the interlayerdielectric layer 154 and the structure shown in FIG. 1H are formed.

Afterwards, one or more first nanowires and one or more second nanowiresare formed, in accordance with some embodiments. As shown in FIGS. 2Aand 4A, the dummy gate structure 134 in the channel regions shown inFIG. 1E is removed, in accordance with some embodiments. As shown inFIGS. 2A and 4A, the first semiconductor layers 118 and the secondsemiconductor layers 120 of the stack structure 122 in the channelregions are exposed, in accordance with some embodiments.

Afterwards, as shown in FIGS. 2B and 4B, a mask element 156 is formed tocover the stack structure 122 over the second fin portion 116, inaccordance with some embodiments. As shown in FIGS. 2B and 4B, the maskelement 156 exposes the stack structure 122 over the first fin portion114, in accordance with some embodiments.

Afterwards, as shown in FIGS. 2B and 4B, an etching process, such as ananisotropic etching process, is performed to remove the secondsemiconductor layers 120 over the first fin portion 114 in the channelregions, in accordance with some embodiments. As shown in FIGS. 2B and4B, the remaining portion of the first semiconductor layers 118 over thefirst fin portion 114 in the channel regions form semiconductor materialwires 158, in accordance with some embodiments.

Afterwards, as shown in FIGS. 2C and 4C, a cladding layer 160 is formedto surround the semiconductor material wire 158 to form a first nanowire162, in accordance with some embodiments. In some embodiments of thepresent disclosure, the cladding layer 160 is made of silicon, silicongermanium, germanium tin, silicon germanium tin, gallium arsenide,indium gallium arsenide, indium arsenide, another suitable material, ora combination thereof. In some embodiments of the present disclosure,the material of the cladding layer 160 is the same as the material ofthe semiconductor material wire 158. In some embodiments of the presentdisclosure,

In some embodiments, the cladding layer 160 is formed using an epitaxialgrowth process. The cladding layer 160 may be formed using a selectiveepitaxial growth (SEG) process, a chemical vapor deposition (CVD)process (e.g., a vapor-phase epitaxy (VPE) process, a low-pressure CVD(LPCVD) process, and/or an ultra-high vacuum CVD (UHV-CVD) process), amolecular beam epitaxy process, another applicable process, or acombination thereof.

As shown in FIG. 4C, the first nanowire 162 includes two first edgeportions 164 adjacent to the two source/drain portions 150 respectively,in accordance with some embodiments. As shown in FIG. 4C, the firstnanowire 162 includes one first central portion 166 between the twofirst edge portions 164, in accordance with some embodiments. As shownin FIG. 4C, the first nanowire 162 is adjacent to the source/drainportions 150, in accordance with some embodiments.

FIG. 2D is an enlarged view of the first nanowire 162 in accordance withsome embodiments of the present disclosure, FIG. 2E is a cross-sectionalview of the first edge portions 164 of the first nanowire 162 inaccordance with some embodiments of the present disclosure, and FIG. 2Fis a cross-sectional view of the first central portion 166 of the firstnanowire 162 in accordance with some embodiments of the presentdisclosure.

As shown in FIGS. 2E and 2F, the first nanowire 162 has a polygonalcross-section, in accordance with some embodiments. Specifically, asshown in FIG. 2E, the two first edge portions 164 have a hexagonalcross-section, in accordance with some embodiments. As shown in FIG. 2F,the first central portion 166 has a quadrilateral cross-section, inaccordance with some embodiments.

In some embodiments of the present disclosure, since the first nanowire162 includes the semiconductor material wire 158 and the cladding layer160, rather than only including the semiconductor material wire 158, thecross-sectional area of the first nanowire 162 is increased. Therefore,in some embodiments of the present disclosure, the current flowingthrough the first nanowire 162 under a given voltage is increased, andthe drain-induced barrier lowering issue is reduced, compared to thenanowire with a circular cross-section or the FinFET transistor.

As shown in FIGS. 2E and 2F, the first nanowires 162 vertically arrangedover the first fin portion 114, and two adjacent first nanowires 162 arespaced apart from each other. However, the embodiments of the presentdisclosure are not limited thereto. In some other embodiments, twoadjacent first nanowires 162 contact each other.

Still referring to FIGS. 2C to 2F, the cross-sectional area of the firstnanowire 162 vary from the edge portion 164 to the central portion 166,in accordance with some embodiments. As shown in FIGS. 2C to 2F, theedge portion 164 of the first nanowire 162 has a first cross-sectionalarea, and the central portion 166 of the first nanowire 162 has a secondcross-sectional area, in accordance with some embodiments. In someembodiments of the present disclosure, the first cross-sectional area isgreater than the second cross-sectional area.

Afterwards, the mask element 156 is removed, in accordance with someembodiments. Afterwards, as shown in FIG. 1I, similar processes areperformed to form second nanowires 168 over the second fin portion 116,in accordance with some embodiments. In some embodiments, the materialof second nanowires 168 is different than the material of first nanowire162. In some embodiments of the present disclosure, the second nanowires168 are made of silicon, silicon germanium, germanium tin, silicongermanium tin, gallium arsenide, indium gallium arsenide, indiumarsenide, another suitable material, or a combination thereof. In someembodiments of the present disclosure, the second nanowires 168 are madeof silicon germanium, and the first nanowires 162 are made of silicon.In some embodiments of the present disclosure, two second source/drainportions 148 are adjacent to the second nanowire 168.

In some embodiments of the present disclosure, the second nanowires 168have the same or similar cross-section or shape as that of the firstnanowire 162. FIGS. 3A and 3B are cross-sectional views of the edgeportion of the second nanowires 168 in accordance with some embodimentsof the present disclosure. FIG. 3A also shows the subsequently formedgate dielectric layer and the gate electrode surrounding the secondnanowires 168 in accordance with some embodiments of the presentdisclosure. As shown in FIG. 3A, the second nanowires 168 also includesa semiconductor material wire 168A and a cladding layer 168B surroundingthe semiconductor material wire 168A. As shown in FIG. 3A, two adjacentsecond nanowires 168 contact each other. However, the embodiments of thepresent disclosure are not limited thereto. In some other embodiments,two adjacent second nanowires 168 are spaced apart from each other.

As shown in FIG. 3B, the direction A1 is the direction parallel to thetop surface of the first fin portion 114, the second fin portion 116 orthe base portion 112, in accordance with some embodiments. As shown inFIG. 3B, the sides S1 and S3 are the slanted sides of the secondnanowires 168, and the side S2 is the vertical side of the secondnanowires 168, in accordance with some embodiments.

In some embodiments of the present disclosure, the side S1 has <111>crystal plane. In some embodiments of the present disclosure, the sideS2 has <110> crystal plane. In some embodiments of the presentdisclosure, the first nanowires 162 have the same or similar crystalplane as that of the second nanowires 168.

As shown in FIG. 3B, the side S3 and the direction A1 intersect at anacute angle θ. In some embodiments of the present disclosure, the acuteangle θ is in a range from about 40 degrees to about 70 degrees, forexample from about 50 degrees to about 60 degrees, or about 54.74degrees.

The term “about” typically means+/−20% of the stated value, moretypically +/−10% of the stated value, more typically +/−5% of the statedvalue, more typically +/−3% of the stated value, more typically +/−2% ofthe stated value, more typically +/−1% of the stated value and even moretypically +/−0.5% of the stated value. The stated value of the presentdisclosure is an approximate value. When there is no specificdescription, the stated value includes the meaning of “about”.

Afterwards, as shown in FIG. 1I, a gate dielectric layer 170, a workfunction layer 172 and a gate electrode layer 174 are sequentiallyformed to surround the first nanowire 162 and the second nanowires 168,in accordance with some embodiments. In some embodiments of the presentdisclosure, the gate dielectric layer 170, the work function layer 172and the gate electrode layer 174 form the gate structure 176 surroundingthe first nanowire 162 and the second nanowires 168. As shown in FIG.1I, the work function layer 172 surrounds the gate dielectric layer 170,and the gate electrode layer 174 surrounds the work function layer 172,in accordance with some embodiments.

As shown in FIG. 1I, a gate dielectric layer 170 surrounds the firstnanowire 162 and the second nanowires 168, in accordance with someembodiments. In some embodiments, the gate dielectric layer 170 is madeof metal oxide, metal nitride, metal silicide, transition metal oxide,transition metal nitride, transition metal silicide, transition metaloxynitride, metal aluminate, zirconium silicate, zirconium aluminate.For example, the material of the gate dielectric layer 170 may include,but is not limited to, LaO, AlO, ZrO, TiO, Ta₂O₅, Y₂O₃, SrTiO₃(STO),BaTiO₃(BTO), BaZrO, HfO₂, HfO₃, HfZrO, HfLaO, HfSiO, HfSiON, LaSiO,AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba,Sr)TiO₃(BST), Al₂O₃, any othersuitable high-k dielectric material, or a combination thereof.

In some embodiments, applicable deposition methods for depositing thegate dielectric layer 170 include a chemical vapor deposition (CVD)process, an atomic layer deposition (ALD) process, a thermal oxidationprocess, a spin-on coating process, other applicable processes, andcombinations thereof.

In some embodiments of the present disclosure, the work function layer172 provides the desired work function for transistors to enhance deviceperformance, including improved threshold voltage. In the embodiments offorming an NMOS transistor, the work function layer 172 can be an N-typemetal capable of providing a work function value suitable for thedevice. The work function value is, for example, equal to or less thanabout 4.5 eV. The n-type metal may include metal, metal carbide, metalnitride, or a combination thereof. For example, the N-type metalincludes tantalum, tantalum nitride, or a combination thereof. In someembodiments, the gate electrode 164 includes the N-type metal.

On the other hand, in the embodiments of forming a PMOS transistor, thework function layer 172 can be a P-type metal capable of providing awork function value suitable for the device. The work function value is,for example, equal to or greater than about 4.8 eV. The P-type metal mayinclude metal, metal carbide, metal nitride, other suitable materials,or a combination thereof. For example, the P-type metal includestitanium, titanium nitride, other suitable materials, or a combinationthereof. In some embodiments, the gate electrode 164 includes the P-typemetal.

The work function layer 172 may also be made of hafnium, zirconium,titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide,zirconium carbide, titanium carbide, aluminum carbide), aluminides,ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides,or a combination thereof.

In some embodiments, the work function layer 172 (such as an N-typemetal) are deposited using an applicable deposition process. Examples ofan applicable deposition process include a PVD process, a platingprocess, a CVD process, other applicable processes, and combinationsthereof.

In some embodiments, the gate electrode layer 174 is made of a suitablemetal material. The suitable metal material may include aluminum,tungsten, gold, platinum, cobalt, other suitable metal materials, analloy thereof, or a combination thereof. In some embodiments of thepresent disclosure, the gate electrode layer 174 is deposited over thework function layer 172 by using, for example, a PVD process, a platingprocess, a CVD process, or the like.

Afterwards, as shown in FIG. 1J, top portions of the work function layer172 and the gate electrode layer 174 are removed, in accordance withsome embodiments. Afterwards, as shown in FIG. 1J, a sacrificial layer178 is formed over the work function layer 172 and the gate electrodelayer 174. In some embodiments of the present disclosure, thesacrificial layer 178 is made of silicon nitride, silicon oxide, siliconoxynitride, another suitable dielectric material, or a combinationthereof.

Afterwards, as shown in FIG. 1K, the interlayer dielectric layer 154 isremoved, in accordance with some embodiments. Afterwards, as shown inFIG. 1L, a patterned dummy material layer 180 is formed to cover aportion of the etch stop layer 152, the spacer elements 140 and thesacrificial layer 178, in accordance with some embodiments. As shown inFIG. 1L, the patterned dummy material layer 180 has an opening 182exposing another portion of the etch stop layer 152, the spacer elements140 and the sacrificial layer 178, in accordance with some embodiments.

Afterwards, as shown in FIG. 1M, an interlayer dielectric layer 184 isformed in the opening 182, in accordance with some embodiments. In someembodiments, the interlayer dielectric layer 184 is made of siliconoxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicateglass (PSG), borophosphosilicate glass (BPSG), fluorinated silicateglass (FSG), low-k material, porous dielectric material, anothersuitable material, or a combination thereof. In some embodiments, theinterlayer dielectric layer 184 is deposited using a CVD process, an ALDprocess, a spin-on process, a spray coating process, another applicableprocess, or a combination thereof.

In some embodiments, a dielectric layer is deposited over the patterneddummy material layer 180 and filled into the opening 182 using achemical vapor deposition (CVD) process, a spin-on process, anotherapplicable process, or a combination thereof. In some embodiments, aplanarization process is performed to thin down the dielectric layer.For example, the dielectric layer is thinned until the patterned dummymaterial layer 180 is exposed. The planarization process may include achemical mechanical polishing (CMP) process, a grinding process, a drypolishing process, an etching process, another applicable process, or acombination thereof. As a result, the interlayer dielectric layer 184and the structure shown in FIG. 1M are formed.

Afterwards, as shown in FIG. 1N, the patterned dummy material layer 180and the portion of the etch stop layer 152 not covered by the interlayerdielectric layer 184 are removed, in accordance with some embodiments.

Afterwards, as shown in FIG. 1O, a barrier layer 186 is conformallydeposited over the interlayer dielectric layer 184, the spacer elements140, the source/drain portions 148 and 150, and the sacrificial layer178, in accordance with some embodiments. In some embodiments of thepresent disclosure, the barrier layer 186 is made of titanium nitride,titanium, another suitable material, or a combination thereof. As shownin FIG. 1O, recesses 188 are formed over the source/drain portions 148and 150, in accordance with some embodiments.

Afterwards, as shown in FIG. 1P, a contact plug 190 is formed in therecesses 188, in accordance with some embodiments. In some embodimentsof the present disclosure, the contact plug 190 is made of a singlelayer or multiple layers of cobalt, copper, aluminum, tungsten, gold,chromium, nickel, platinum, titanium, iridium, rhodium, an alloythereof, a combination thereof, or another conductive material.

In some embodiments of the present disclosure, a contact material layer(not shown in this figure) is deposited over the barrier layer 186 andfilled into the recesses 188. In some embodiments, the applicabledeposition methods for depositing the contact material layer include achemical vapor deposition (CVD) process, a physical vapor deposition(PVD) process, and other applicable methods.

Afterwards, in some embodiments, a planarization process is performed tothin down the contact material layer and the barrier layer 186. Forexample, the contact material layer and the barrier layer 186 arethinned until the sacrificial layer 178 is exposed. The planarizationprocess may include a chemical mechanical polishing (CMP) process, agrinding process, a dry polishing process, an etching process, anotherapplicable process, or a combination thereof. As a result, the contactplug 190 and the semiconductor device structure 100 shown in FIG. 1P areformed. In some embodiments of the present disclosure, the contact plugs190 are electrically connected to the source/drain portion 148 and/orthe source/drain portion 150.

It should be noted that the exemplary embodiment set forth in FIGS.1A-1P is merely for the purpose of illustration. In addition to theembodiment set forth in FIGS. 1A-1P, the nanowire may be formed byanother method as shown in FIGS. 5A-5B. This will be described in moredetail in the following description. Therefore, the present disclosureis not limited to the exemplary embodiment shown in FIGS. 1A-1P.

Note that the same or similar elements or layers corresponding to thoseof the semiconductor device are denoted by like reference numerals. Insome embodiments, the same or similar elements or layers denoted by likereference numerals have the same meaning and will not be repeated forthe sake of brevity.

As shown in FIG. 5A, after the semiconductor material wires, such as thesemiconductor material wires 158, are formed, and before forming thecladding layer 160, an outer portion of the semiconductor material wire158 is removed by an etching process, such as an anisotropic etchingprocess, in accordance with some embodiments. As shown in FIG. 5A, aportion of the semiconductor material wire 158 remains, in accordancewith some embodiments.

As shown in FIG. 5B, after the semiconductor material wire 158 ispartially etched and partially removed, the cladding layer 160 is formedto surround the remaining portion of the semiconductor material wire 158to form the first nanowire 162, in accordance with some embodiments. Asshown in FIG. 5B, a portion of the semiconductor material wire 158 has athickness that is less than that of the first source/drain portion 148.

FIG. 6A is a top view of a semiconductor device structure 600A inaccordance with some cases. In some cases, the semiconductor devicestructure 600A includes a P-type FET 604A and an N-type FET 606A. Insome cases, the P-type FET 604A includes three or more fin structures608A which use a portion of the fin structures 608A or a nanowire with acircular cross-section as a channel. In some cases, the N-type FET 606Aincludes three or more fin structures 610A which use a portion of thefin structures 610A or a nanowire with a circular cross-section as achannel. In addition, a dielectric layer 612 is positioned between theP-type FET 604A and the N-type FET 606A. In addition, one or more gatestructures 602 traverse through the fin structures 608A and 610A.

FIG. 6B is a top view of a semiconductor device structure 600B inaccordance with some embodiments. In some embodiments, the semiconductordevice structure 600B includes a P-type FET 604B and an N-type FET 606B.In some embodiments, the P-type FET 604B includes two fin structures608B which use a nanowire with a polygonal cross-section as a channel.In some embodiments, the N-type FET 606B includes two fin structures610B which use a nanowire with a polygonal cross-section as a channel.

Since the nanowire in the embodiments of the present disclosure has apolygonal cross-section, the current flowing through the nanowire in theembodiments of the present disclosure under a given voltage isincreased, and the drain-induced barrier lowering issue is reduced,compared to the device using nanowire with a circular cross-section orthe FinFET transistor. Therefore, the P-type FET 604B and the N-type FET606B may use fewer fin structures 606B and 608B and fewer trackscompared to the device using nanowire with a circular cross-section orthe FinFET transistor.

FIG. 6C is a top view of a semiconductor device structure 600C inaccordance with some embodiments. In some embodiments, the semiconductordevice structure 600C includes a P-type FET 604C and an N-type FET 606C.In some embodiments, the P-type FET 604C includes one fin structure 608Cwhich uses a nanowire with a polygonal cross-section as a channel. Insome embodiments, the N-type FET 606C includes one fin structure 610Cwhich uses a nanowire with a polygonal cross-section as a channel.

Since the nanowire in the embodiments of the present disclosure has apolygonal cross-section, the current flowing through the nanowire in theembodiments of the present disclosure under a given voltage isincreased, and the drain-induced barrier lowering issue is reduced,compared to the device using nanowire with a circular cross-section orthe FinFET transistor. Therefore, the P-type FET 604C and the N-type FET606C may use fewer fin structures 606C and 608C and fewer trackscompared to the device using nanowire with a circular cross-section orthe FinFET transistor.

Embodiments of the disclosure use nanowire with a polygonalcross-section. Therefore, the current flowing through the nanowire inthe embodiments of the present disclosure under a given voltage isincreased, and the drain-induced barrier lowering issue is reduced,compared to the device using nanowire with a circular cross-section orthe FinFET transistor.

Embodiments of the disclosure are not limited and may be applied tofabrication processes for any suitable technology generation. Varioustechnology generations include a 20 nm node, a 16 nm node, a 10 nm node,or another suitable node.

In accordance with some embodiments, a semiconductor device structure isprovided. The semiconductor device structure includes a substrateincluding a first fin portion and a first nanowire over the first finportion. The first nanowire has a polygonal cross-section. Thesemiconductor device structure also includes a first gate structuresurrounding the first nanowire, and two first source/drain portionsadjacent to the first nanowire.

In accordance with some embodiments, a semiconductor device structure isprovided. The semiconductor device structure includes a substrateincluding a fin portion, a nanowire over the fin portion, and a gatestructure surrounding the nanowire, and two source/drain portionsadjacent to the nanowire. The nanowire includes two edge portionsadjacent to the two source/drain portions, respectively, and a centralportion between the two edge portions. The nanowire has across-sectional area varying from the edge portion to the centralportion.

In accordance with some embodiments, a method for forming asemiconductor device structure is provided. The method includesproviding a substrate having a base portion and a fin portion over thebase portion. The fin portion has a channel region and a source/drainregion. The method also includes forming a stack structure over the finportion. The stack structure includes a first semiconductor layer and asecond semiconductor layer vertically stacked over the fin portion. Themethod further includes forming two source/drain portions in the stackstructure at the source/drain region, and removing a portion of thesecond semiconductor layer in the channel region. The remaining portionof the first semiconductor layer in the channel region forms asemiconductor material wire. The method also includes forming a claddinglayer surrounding the semiconductor material wire to form a nanowire.The nanowire has a polygonal cross-section. The method further includesforming a gate structure surrounding the nanowire.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

1. A semiconductor device structure, comprising: a substrate comprisinga first fin portion; a first nanowire over the first fin portion,wherein the first nanowire has a polygonal cross-section; a first gatestructure surrounding the first nanowire; and two first source/drainportions adjacent to the first nanowire, wherein the first nanowirecomprises: two first edge portions adjacent to the two firstsource/drain portions respectively; and a first central portion betweenthe two first edge portions, wherein the two first edge portions have ahexagonal cross-section, and the first central portion has aquadrilateral cross-section.
 2. (canceled)
 3. The semiconductor devicestructure as claimed in claim 1, wherein the substrate further comprisesa second fin portion adjacent to the first fin portion, wherein thesemiconductor device structure further comprises: a second nanowire overthe second fin portion, wherein the second nanowire is made of adifferent material than that of the first nanowire, and the secondnanowire has a polygonal cross-section; a second gate structuresurrounding the second nanowire; and two second source/drain portionsadjacent to the second nanowire.
 4. The semiconductor device structureas claimed in claim 3, wherein the second nanowire comprises: two secondedge portions adjacent to the two second source/drain portionsrespectively; and a second central portion between the two second edgeportions, wherein the two second edge portions have a hexagonalcross-section, and the second central portion has a quadrilateralcross-section.
 5. The semiconductor device structure as claimed in claim1, further comprising: a plurality of first nanowires verticallyarranged over the first fin portion, wherein two adjacent firstnanowires contact each other.
 6. The semiconductor device structure asclaimed in claim 1, further comprising: a plurality of first nanowiresvertically arranged over the first fin portion, wherein two adjacentfirst nanowires are spaced apart from each other.
 7. The semiconductordevice structure as claimed in claim 1, wherein the first nanowirecomprises: a semiconductor material wire; and a cladding layersurrounding the semiconductor material wire.
 8. The semiconductor devicestructure as claimed in claim 7, wherein the semiconductor material wirehas a thickness that is less than that of the first source/drainportion.
 9. The semiconductor device structure as claimed in claim 1,wherein the first gate structure comprises: a first gate dielectriclayer surrounding the first nanowire; and a first gate electrodesurrounding the first gate dielectric layer.
 10. The semiconductordevice structure as claimed in claim 3, wherein the second gatestructure comprises: a second gate dielectric layer surrounding thesecond nanowire; and a second gate electrode surrounding the second gatedielectric layer.
 11. A semiconductor device structure, comprising: asubstrate comprising a fin portion; a nanowire over the fin portion; agate structure surrounding the nanowire; and two source/drain portionsadjacent to the nanowire, wherein the nanowire comprises: two edgeportions adjacent to the two source/drain portions respectively; and acentral portion between the two edge portions, wherein the nanowire hasa cross-sectional area varying from the edge portion to the centralportion, wherein the edge portion has a first cross-sectional area, andthe central portion has a second cross-sectional area, wherein the firstcross-sectional area is greater than the second cross-sectional area.12. (canceled)
 13. The semiconductor device structure as claimed inclaim 11, wherein the two edge portions have a hexagonal cross-section,and the central portion has a quadrilateral cross-section.
 14. Thesemiconductor device structure as claimed in claim 11, furthercomprising: a plurality of nanowires vertically arranged over the finportion, wherein each two adjacent nanowires are in contact with eachother.
 15. The semiconductor device structure as claimed in claim 11,further comprising: a plurality of nanowires vertically arranged overthe fin portion, wherein two adjacent nanowires are spaced apart fromeach other.
 16. A method for forming a semiconductor device structure,comprising: providing a substrate having a base portion and a finportion over the base portion, wherein the fin portion has a channelregion and a source/drain region; forming a stack structure over the finportion, wherein the stack structure comprises a first semiconductorlayer and a second semiconductor layer vertically stacked over the finportion; forming two source/drain portions in the stack structure at thesource/drain region; removing a portion of the second semiconductorlayer in the channel region, wherein a remaining portion of the firstsemiconductor layer in the channel region forms a semiconductor materialwire; forming a cladding layer surrounding the semiconductor materialwire in the channel region to form a nanowire, wherein the nanowire hasa polygonal cross-section; and forming a gate structure surrounding thenanowire.
 17. The method as claimed in claim 16, wherein before formingthe cladding layer, the method further comprises: removing an outerportion of the semiconductor material wire, and leaving a remainingportion of the semiconductor material wire.
 18. The method as claimed inclaim 17, wherein the cladding layer surrounds the remaining portion ofthe semiconductor material wire to form the nanowire.
 19. The method asclaimed in claim 16, wherein before forming the source/drain portions,the method further comprises: forming a dummy gate structure coveringthe stack structure.
 20. The method as claimed in claim 16, whereinbefore removing the portion of the second semiconductor layer in thechannel region, the method further comprises: removing the dummy gatestructure in the channel region.
 21. The semiconductor device structureas claimed in claim 3, wherein the first gate structure is in directcontact with the second gate structure.
 22. The semiconductor devicestructure as claimed in claim 3, wherein an acute angle between aslanted side of the second nanowire and a direction parallel to a topsurface of the first fin portion is in a range from about 40 degrees toabout 70 degrees.